In the field of electrical system, e.g. a monitor control system, a signal of a desired pulse width is frequently needed to be the input signal of other circuits of the electrical system.
One of the conventional approaches uses an external resistor-capacitor circuit together with a monostable multivibrator, i.e. IC 74LS221, which responds to a trigger signal to output a signal of the desired pulse width at the output terminal of the monostable multivibrator. The desired pulse width of the signal is determined by the RC constant of the resistor-capacitor circuit. However, this type of analog approach, on one hand, is not easily implemented on a digital integrated circuit since the circuit of the monostable multivibrator is in analog nature. On the other hand, the analog approach is sensitive to the noise signal. Other related prior arts include U.S. Pat. Nos. 4,598,412, 4,994,687, 5,059,812, 5,124,573 and 5,422,585.
U.S. Pat. No. 4,598,412 discloses a binary digital data signal reproducing circuit. The binary digital data signal is prepared at a transmitter side and is converted to a bipolar signal which is sent out to a digital transmission line. Due to waveform distortion during transmission, the signal is received at a receiver side, which is the input terminal of the pulse detect circuit. The object of Yoshida is to generate the binary digital data signal at the Q terminal of the Flip-Flop, which is a reproduction of the binary digital data signal. Therefore, each bit of the signal "i" has a length T which is totally identical to that of each bit of the signal "a". Due to the circuit construction of Yoshida, the bit length T of binary digital data signal "i" is fixed and can not be altered. Furthermore, the timing relation between the signal "i" and "a" is an asynchronous one, which is the result of the application of the clock signal generated from the clock pulse generator 12.
U.S. Pat. No. 5,124,573 discloses a circuit for reducing or expanding the duty cycle of a clock input signal. It is important to note Wong uses the set terminal of a Reset Dominant latch for receiving the clock input signal, and delay signal is dependent both on the clock out signal and clock in signal. Furthermore, the delay block of Wong is so complicated that the delay time Td are dependent on many factors, for instance, the turn on voltage of T6, the voltage pick off point of the charge voltage at node 62, RC time constant of cell 50 and many others.
The apparatus of U.S. Pat. No. 5,422,585 includes a flip-flop, a delay circuit and a clear circuit. The flip-flop, in response to a first trigger signal, outputs the output signal at an output terminal. The delay circuit generates a second trigger signal by delaying the output signal for a predetermined amount of time. The clear circuit, in response to the second trigger signal, generates a clear signal to the flip-flop in order to clear the output signal. The desired pulse width of the output signal is controlled by the predetermined amount of time delayed in the delay circuit.